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december 2015 docid028783 rev 1 1 / 12 this is information on a product in full production. www.st.com STFI7LN80K5 n - channel 800 v, 0.95 typ., 5 a mdmesh? k5 power mosfet in a i2pakfp package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d STFI7LN80K5 800 v 1.15 5 a ? industrys lowest r ds(on) x area ? industrys best figure of merit (fom) ? ultra - low gate charge ? 100% avalanche tested ? zener - protected applications ? switching applications description this very high voltage n - channel power mosfet is designed using mdmesh? k5 technology based on an innovative proprietary vertical structure. the result is a dramatic r eduction in on - resistance and ultra - low gate charge for applications requiring superior power density and high efficiency. table 1: device summary order code marking packa ge packing STFI7LN80K5 7ln80k5 i2pakfp (to - 281) tube 1 2 3 i 2 p akf p ( t o-281) am15572v1_no_tab d(2) g(1) s(3)
contents STFI7LN80K5 2 / 12 docid028783 rev 1 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteri stics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 8 4 package information ................................ ................................ ....... 9 4.1 i2pakfp (to - 281) package information ................................ ........... 9 5 revision history ................................ ................................ ............ 11
STFI7LN80K5 electrical ratings docid028783 rev 1 3 / 12 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 30 v i d (1) drain current (continuous) at t c = 25 c 5 a i d (1) drain current (continuous) at t c = 100 c 3.4 a i d (2) drain current (pulsed) 20 a p tot total dissipation at t c = 25 c 25 w v iso insulation withstand voltage (rms) from all three leads to external heat sink (t=1 s; t c =25 c) 2500 v dv/dt (3) peak diode recovery voltage slope 4.5 v/ns dv/dt (4) mosfet dv/dt ruggedness 50 t stg storage temperature - 55 to 150 c t j operating junction temperature notes: (1) limited by maximum junction temperature. (2) pulse width limited by safe operating area. (3) i sd 5 a, di/dt 100 a/s; v ds peak < v (br)dss, v dd = 640 v (4) v ds 640 v table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case 5 c/w r thj - amb thermal resistance junction - ambient 62.5 c/w table 4: avalanche characteristics symbol parameter value unit i ar avalanche current, repetitive or not repetitive (pulse width limited by t jmax ) 1.5 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 200 mj
electrical characteristics STFI7LN80K5 4 / 12 docid028783 rev 1 2 electrical characteristics t c = 25 c unless otherwise specified table 5: on/off - state symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 800 v i dss zero gate voltage drain current v gs = 0 v, v ds = 800 v 1 a v gs = 0 v, v ds = 800 v t c = 125 c 50 a i gss gate body leakage current v ds = 0 v, v gs = 20 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 4 5 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 2.5 a 0.95 1.15 ? table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 v - 270 - pf c oss output capacitance - 22 - pf c rss reverse transfer capacitance - 0.5 - pf c o(er) (1) equivalent capacitance energy related v ds = 0 to 640 v, v gs = 0 v - 17 - nc c o(tr) (2) equivalent capacitance time related - 48 - nc r g intrinsic gate resistance f = 1 mhz, i d =0 a - 7.5 - ? q g total gate charge v dd = 640 v, i d = 5 a v gs = 10 v see ( figure 15: "test circuit for gate charge behavior" ) - 12 - nc q gs gate - source charge - 2.6 - nc q gd gate - drain charge - 8.6 - nc notes: (1) energy related is defined as a constant equivalent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss (2) time related is defined as a constant equivalent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss table 7: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 400 v, i d =2.5 a, r g = 4.7 ? v gs = 10 v see ( figure 14: "test circuit for resistive load switching times" and figure 19: "switching time waveform" ) - 9.3 - ns t r rise time - 6.7 - ns t d(off) turn - off delay time - 23.6 - ns t f fall time - 17.4 - ns
STFI7LN80K5 electrical charact eristics docid028783 rev 1 5 / 12 table 8: source - drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 5 a i sdm (1) source - drain current (pulsed) - 20 a v sd (2) forward on voltage i sd = 5 a, v gs = 0 v - 1.6 v t rr reverse recovery time i sd = 5 a, di/dt = 100 a/s, v dd = 60 v see figure 16: "test circuit for inductive load switching and diode recovery times" - 276 ns q rr reverse recovery charge - 2.13 c i rrm reverse recovery current - 15.4 a t rr reverse recovery time i sd = 5 a, di/dt = 100 a/s v dd = 60 v, t j = 150 c see figure 16: "test circuit for inductive load switching and diode recovery times" - 402 ns q rr reverse recovery charge - 2.79 c i rrm reverse recovery current - 13.9 a notes: (1) pulse width limited by safe operating area (2) pulsed: pulse duration = 300 s, duty cycle 1.5% table 9: gate - source zener diode symbol parameter test conditions min. typ. max. unit v (br)gso gate - source breakdown voltage i gs = 1ma, i d = 0 a 30 - - v the built - in back - to - back zener diodes are specifically designed to enhance the esd performance of the device. the zener voltage facilitates efficient and cost - effective device integrity protection,thus eliminating the need for additional external componentry.
electrical characteristics STFI7LN80K5 6 / 12 docid028783 rev 1 2.2 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : outp ut characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance
STFI7LN80K5 electrical characteristics docid028783 rev 1 7 / 12 figure 8 : capacitance variations figure 9 : normalized gate threshold voltage vs temperature figure 10 : normalized v (br)dss vs temperature figure 11 : normalized on - resistance vs temperature figure 12 : source - drain diode forward characteristics figure 13 : maximum avalanche energy vs starting t j
test circuits STFI7LN80K5 8 / 12 docid028783 rev 1 3 test circuits figure 14 : test circuit for resistive load switching times figure 15 : test circuit for gate charge behavior figure 16 : test circuit for inductive load switching and diode recovery times figure 17 : unclamped inductive load test circuit figure 18 : unclamped inductive waveform figure 19 : switchi ng time waveform
STFI7LN80K5 package information docid028783 rev 1 9 / 12 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 i2pakfp (to - 281) package information figure 20 : i2pakfp (to - 281) package outline 8291506 re v . c
package information STFI7LN80K5 10 / 12 docid028783 rev 1 table 10: i2pakfp (to - 281) mechanical data dim. mm min. typ. max. a 4.40 4.60 b 2.50 2.70 d 2.50 2.75 d1 0.65 0.85 e 0.45 0.70 f 0.75 1.00 f1 1.20 g 4.95 5.20 h 10.00 10.40 l1 21.00 23.00 l2 13.20 14.10 l3 10.55 10.85 l4 2.70 3.20 l5 0.85 1.25 l6 7.50 7.60 7.70
STFI7LN80K5 revision history docid028783 rev 1 11 / 12 5 revision history table 11: document revision history date revision changes 15 - dec - 2015 1 first release.
STFI7LN80K5 12 / 12 docid028783 rev 1 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers s hould obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, select ion, and use of st products and st assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics C all rights reserved

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